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ltc3788 1 3788fc 15nf 4.7f 2.7k 12.1k 12.1k v out 12v at 5a v out 24v at 3a v in 4.5v to 12v start-up voltage operates through transients down to 2.5v v in 0.1f 100pf 0.1f 220f 220f tg1 boost1 sw1 bg1 freq ss1 sgnd ss2 sense1 + sense1 ? vfb1 ith1 vbias ltc3788 intv cc pllin/mode tg2 boost2 sw2 bg2 sense2 + sense2 ? vfb2 ith2 pgnd 0.1f 15nf 8.66k 220pf 232k 0.1f 4.7f 110k 3788 ta01a 220f 3.3h 1.25h 3m 4m typical a pplica t ion descrip t ion 2-phase, dual output synchronous boost controller the lt c ? 3788 is a high performance 2-phase dual synchronous boost converter controller that drives all n-channel power mosfets. synchronous rectification increases efficiency, reduces power losses and eases thermal requirements, allowing the ltc3788 to be used in high power boost applications. a constant-frequency current mode architecture allows a phase-lockable frequency of up to 850 khz. opti-loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the ltc3788 features a precision 1.2 v reference and dual power good output indicators. a 4.5 v to 38 v input supply range encompasses a wide range of system architectures and battery chemistries. independent ss pins for each controller ramp the output voltages during start-up. the pllin/mode pin selects among burst mode ? operation, pulse-skipping mode or continuous inductor current mode at light loads. for a leaded 28- lead ssop package with a fixed current limit and one pgood output, without phase modulation or a clock output, see the ltc3788-1 data sheet. l, lt , lt c , lt m , linear technology, burst mode, opti-loop, polyphase and the linear logo are registered trademarks and no r sense and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u . s. patents, including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258. fea t ures a pplica t ions n synchronous operation for highest efficiency and reduced heat dissipation n wide input range: 4.5v to 38v (40v abs max) and operates down to 2.5v after start-up n output voltages up to 60v n 1% 1.2v reference voltage n r sense or inductor dcr current sensing n 100% duty cycle capability for synchronous mosfet n low quiescent current: 125a n phase-lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n selectable current limit n adjustable output voltage soft-start n power good output voltage monitors n low shutdown current i q : < 8a n internal ldo powers gate drive from vbias or extv cc n thermally enhanced low profile 32-pin 5mm 5mm qfn package n industrial n automotive n medical n military efficiency and power loss vs output current output current (a) 40 efficiency (%) power loss (mw) 50 60 70 80 3788 ta01b 30 20 10 0 90 100 10 100 1000 1 0.1 10000 0.01 0.1 1 10 v in = 12v v out = 24v burst mode operation figure 9 circuit 0.0001 0.001 0.00001
ltc3788 2 3788fc p in c on f igura t ion the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c, vbias = 12v, unless otherwise noted (note 2). a bsolu t e maxi m u m r a t ings vbias ........................................................ C 0.3 v to 40 v boost 1, boost2 ...................................... C 0. 3 v to 76 v sw 1, sw2 .................................................. C 0. 3 v to 70 v run 1, run 2 ................................................ C 0. 3 v to 8v ma ximum current sourced into pin from source > 8v ............................................. 10 0 a pgood 1, pgood2, pllin / mode ............... C 0. 3 v to 6v intv cc , (boost 1- sw 1, boost 2- sw 2) ...... C 0. 3 v to 6v extv cc ........................................................ C 0.3 v to 6v sense 1 + , sense 1 C , sense 2 + , sense 2 C .................................... C 0.3 v to 40 v sense 1 + C sense 1 C , sense 2 + C sense 2 C ................................. C 0.3 v to 0.3 v i lim , ss 1, ss 2, ith 1, ith 2, freq , phasmd , vfb 1, vfb 2 ........................... C 0. 3 v to intv cc operating junction temperature range .... C 4 0 c to 125 c storage temperature range .................. C 6 5 c to 125 c (notes 1, 3) 32 33 gnd 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1sense1 ? freq phasmd clkout pllin/mode sgnd run1 run2 boost1 bg1 vbias pgnd extv cc intv cc bg2 boost2 sense1 + vfb1 ith1 ss1 ilim pgood1 sw1 tg1 sense2 ? sense2 + vfb2 ith2 ss2 pgood2 sw2 tg2 t jmax = 125c, ja = 34c/w exposed pad (pin 33) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3788euh#pbf ltc3788euh#trpbf 3788 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc3788iuh#pbf ltc3788iuh#trpbf 3788 32-lead (5mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units main control loop vbias chip bias voltage operating range 4.5 38 v v fb1,2 regulated feedback voltage i th = 1.2v (note 4) l 1.188 1.200 1.212 v i fb1,2 feedback current (note 4) 5 50 na v reflnreg reference line voltage regulation vbias = 6v to 38v 0.002 0.02 %/ v
ltc3788 3 3788fc e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c, vbias = 12v, unless otherwise noted (note 2). symbol parameter conditions min typ max units v loadreg output voltage load regulation (note 4) measured in servo loop; ?i th voltage = 1.2v to 0.7v l 0.01 0.1 % measured in servo loop; ?i th voltage = 1.2v to 2v l C0.01 C0.1 % g m1,2 error amplifier transconductance i th = 1.2v 2 mmho i q input dc supply current (note 5) pulse-skipping or forced continuous mode (one channel on) run1 = 5v and run2 = 0v or run1 = 0v and run2 = 5v; v fb1(2) = 1.25v (no load) 0.9 ma pulse-skipping or forced continuous mode (both channels on) run1,2 = 5v; v fb1,2 = 1.25v (no load) 1.2 ma sleep mode (one channel on) run1 = 5v and run2 = 0v or run1 = 0v and run2 = 5v; v fb1(2) = 1.25v (no load) 125 190 a sleep mode (both channels on) run1,2 = 5v; v fb1,2 = 1.25v (no load) 200 300 a shutdown run1,2 = 0v 8 20 a uvlo intv cc undervoltage lockout thresholds v intvcc ramping up l 4.1 4.3 v v intvcc ramping down l 3.6 3.8 v v run1,2 run pin on threshold v run rising l 1.18 1.28 1.38 v v runhys run pin hysteresis 100 mv i run1,2 run pin hysteresis current v run > 1.28v 4.5 a i run1,2 run pin current v run < 1.28v 0.5 a i ss1,2 soft-start charge current v ss = gnd 7 10 13 a v sense(max) maximum current sense threshold v fb = 1.1v, i lim = intv cc l 90 100 110 mv v fb = 1.1v, i lim = float l 68 75 82 mv v fb = 1.1v, i lim = gnd l 42 50 56 mv v sense(cm) sense pins common mode range (boost converter input supply voltage v in ) 2.5 38 v i sense1,2 + sense + pin current v fb = 1.1v, i lim = float 200 300 a i sense1,2 C sense C pin current v fb = 1.1v, i lim = float 1 a t r(tg1,2) top gate rise time c load = 3300pf (note 6) 20 ns t f (tg1,2) top gate fall time c load = 3300pf (note 6) 20 ns t r(bg1,2) bottom gate rise time c load = 3300pf (note 6) 20 ns t f(bg1,2) bottom gate fall time c load = 3300pf (note 6) 20 ns r up(tg1,2) top gate pull-up resistance 1.2 r dn(tg1,2) top gate pull-down resistance 1.2 r up(tg1,2) bottom gate pull-up resistance 1.2 r dn(tg1,2) bottom gate pull-down resistance 1.2 t d(tg/bg) top gate off to bottom gate on switch-on delay time c load = 3300pf (each driver) 70 ns t d(bg/tg) bottom gate off to top gate on switch-on delay time c load = 3300pf (each driver) 70 ns df max(bg1,2) maximum bg duty factor 96 %
ltc3788 4 3788fc symbol parameter conditions min typ max units t on(min) minimum bg on-time (note 7) 110 ns intv cc linear regulator v intvccvin internal v cc voltage 6v < vbias < 38v, v extvcc = 0v 5.2 5.4 5.6 v v ldovin intv cc load regulation i cc = 0ma to 50ma, v extvcc = 0v 0.5 2 % v intvccext internal v cc voltage v extvcc = 6v 5.2 5.4 5.6 v v ldoext intv cc load regulation i cc = 0ma to 40ma, v extvcc = 6v 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.8 5 v v ldohys extv cc hysteresis 250 mv oscillator and phase-locked loop f prog programmable frequency r freq = 25k 105 khz r freq = 60k 335 400 465 khz r freq = 100k 760 khz f low lowest fixed frequency v freq = 0v 320 350 380 khz f high highest fixed frequency v freq = intv cc 485 535 585 khz f sync synchronizable frequency pllin/mode = external clock l 75 850 khz pgood1 and pgood2 outputs v pgl pgood voltage low i pgood = 2ma 0.2 0.4 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative C12 C10 C8 % hysteresis 2.5 % v fb ramping positive 8 10 12 % hysteresis 2.5 % t pgood(delay) pgood delay pgood going high to low 25 s boost1 and boost2 charge pump i boost1,2 boost charge pump available output current v sw1,2 = 12v; v boost1,2 C v sw1,2 = 4.5v; freq = 0v, forced continuous or pulse-skipping mode 55 a e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, other wise specifications are at t a = 25c, vbias = 12v, unless otherwise noted (note 2). note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3788 is tested under pulsed load conditions such that t j t a . the ltc3788e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3788i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja = 34c/w. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc3788 is tested in a feedback loop that servos v fb to the output of the error amplifier while maintaining i th at the midpoint of the current limit range. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: see minimum on-time considerations in the applications information section.
ltc3788 5 3788fc typical p er f or m ance c harac t eris t ics load step burst mode operation load step forced continuous mode load step pulse-skipping mode efficiency and power loss vs output current efficiency and power loss vs output current efficiency vs input voltage output current (a) 40 efficiency (%) power loss (mw) 50 60 70 80 10 3788 g01 30 20 10 0 90 100 10 100 1000 1 0.1 10000 0.01 0.1 1 burst efficiency pulse-skipping efficiency ccm efficiency burst loss pulse-skipping loss ccm loss v in = 12v v out = 24v figure 9 circuit output current (a) 40 efficiency (%) power loss (mw) 50 60 70 80 3788 g02 30 20 10 0 90 100 10 100 1000 1 0.1 10000 0.01 0.1 1 10 burst efficiency burst loss v in = 12v v out = 24v burst mode operation figure 9 circuit 0.0001 0.001 0.00001 input voltage (v) 0 90 efficiency (%) 92 94 96 5 10 15 20 98 100 91 93 95 97 99 25 3788 g03 v out = 12v i load = 2a figure 9 circuit v out = 24v v out 500mv/div inductor current 5a/div load step 2a/div v in = 12v v out = 24v figure 9 circuit 200s/div 3788 g04 v out 500mv/div inductor current 5a/div load step 2a/div v in = 12v v out = 24v figure 9 circuit 200s/div 3788 g05 v out 500mv/div inductor current 5a/div load step 2a/div v in = 12v v out = 24v figure 9 circuit 200s/div 3788 g06
ltc3788 6 3788fc typical p er f or m ance c harac t eris t ics inductor current at light load soft start-up regulated feedback voltage vs temperature pulse-skipping mode burst mode operation 5a/div forced continuous mode v in = 12v v out = 24v i load = 200a figure 9 circuit 5s/div 3788 g07 0v v out 5v/div v in = 12v v out = 24v figure 9 circuit 20ms/div 3788 g08 temperature (c) ?45 regulated feedback voltage (v) 1.209 30 3788 g09 1.200 1.194 ?20 5 55 1.191 1.188 1.212 1.206 1.203 1.197 80 105 130 shutdown current vs temperature soft-start pull-up current vs temperature shutdown current vs input voltage temperature (c) ?45 soft-start current (a) 10.5 30 3788 g10 ?20 5 55 9.0 11.0 10.0 9.5 80 105 130 ?45 30 ?20 5 55 80 105 130 temperature (c) shutdown current (a) 7.0 9.5 10.0 10.5 11.0 6.0 8.5 6.5 9.0 5.5 5.0 8.0 7.5 3788 g11 v in = 12v 0 15 5 10 20 25 30 35 40 input voltage (v) shutdown current (a) 10 20 5 0 15 3788 g12
ltc3788 7 3788fc typical p er f or m ance c harac t eris t ics quiescent current vs temperature extv cc switchover and intv cc voltages vs temperature intv cc line regulation shutdown (run) threshold vs temperature undervoltage lockout threshold vs temperature intv cc vs intv cc load current temperature (c) ?45 quiescent current (a) 30 3788 g13 140 120 ?20 5 55 110 100 170 160 150 130 80 105 130 v in = 12v v fb = 1.25v run2 = gnd temperature (c) ?45 run pin voltage (v) 30 3788 g14 1.25 1.15 ?20 5 55 1.10 1.40 1.35 1.30 1.20 80 105 130 run falling run rising ?45 30 ?20 5 55 80 105 130 temperature (c) intv cc voltage (v) 3.6 4.1 4.2 4.3 4.4 3.9 3.5 4.0 3.4 3.8 3.7 3788 g15 intv cc rising intv cc falling 0 15 5 10 20 25 30 35 40 input voltage (v) intv cc voltage (v) 4.7 5.2 5.3 5.4 5.5 5.0 4.6 5.1 4.5 4.9 4.8 3788 g16 intv cc load current (ma) 0 intv cc voltage (v) 5.35 5.40 5.45 140 5.30 5.25 40 80 20 180 60 100 160 120 200 5.20 5.00 5.10 5.05 5.15 5.50 3788 g17 extv cc = 0v extv cc = 6v v in = 12v temperature (c) ?45 4.0 extv cc and intv cc voltage (v) 4.2 4.6 4.8 5.0 6.0 5.4 5 55 80 4.4 5.6 5.8 5.2 ?20 30 105 130 3788 g18 extv cc rising extv cc falling intv cc
ltc3788 8 3788fc sense pin input current vs temperature oscillator frequency vs temperature maximum current sense threshold vs i th voltage sense pin input current vs v sense voltage sense pin input current vs i th voltage oscillator frequency vs input voltage typical p er f or m ance c harac t eris t ics temperature (c) ?45 300 frequency (khz) 350 600 450 5 55 80 500 550 400 ?20 30 105 130 3788 g19 freq = gnd freq = intv cc 15 5 10 20 25 30 35 40 input voltage (v) oscillator frequency (khz) 344 354 356 358 360 350 342 352 340 348 346 3788 g20 freq = gnd i th voltage (v) 0 maximum current sense voltage (mv) 80 120 100 0.6 1.0 3788 g21 40 0 0.2 0.4 0.8 1.2 1.4 ?40 60 20 ?20 ?60 i lim = gnd i lim = float i lim = intv cc burst mode operation pulse skipping mode forced continuous mode temperature (c) ?45 sense current (a) 5 55 80 0 80 40 160 200 240 120 20 100 60 180 220 260 140 ?20 30 105 130 3788 g22 sense + pin sense ? pin v sense = 12v i lim = float i th voltage (v) 0 sense current (a) 1 2 2.5 0 80 40 160 200 240 120 20 100 60 180 220 260 140 0.5 1.5 3 3788 g23 sense + pin sense ? pin v sense = 12v i lim = intv cc i lim = float i lim = gnd i lim = intv cc i lim = float i lim = gnd v sense common mode voltage (v) 2.5 sense current (a) 17.5 27.5 32.5 0 80 40 160 200 240 120 20 100 60 180 220 260 140 7.5 12.5 22.5 37.5 3788 g24 sense + pin sense ? pin i lim = intv cc i lim = float i lim = gnd i lim = intv cc i lim = float i lim = gnd
ltc3788 9 3788fc typical p er f or m ance c harac t eris t ics p in func t ions sense1 C , sense 2 C ( pin 1, pin 9): negative current sense comparator input. the (C) input to the current comparator is normally connected to the negative terminal of a cur- rent sense resistor connected in series with the inductor. the common mode voltage range on these pins is 2.5v to 38v (abs max). freq (pin 2): the frequency control pin for the internal vco. connecting the pin to gnd forces the vco to a fixed low frequency of 350 khz. connecting the pin to intv cc forces the vco to a fixed high frequency of 535 khz. the frequency can be programmed from 50 khz to 900khz by connecting a resistor from the freq pin to gnd. the resistor and an internal 20 a source current create a volt- age used by the internal oscillator to set the frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. phasmd (pin 3): this pin can be floated, tied to sgnd, or tied to intv cc to program the phase relationship between the rising edges of bg1 and bg2, as well as the phase relationship between bg1 and clkout. clkout (pin 4): a digital output used for daisychaining multiple ltc3788 ics in multiphase systems. the phasmd pin voltage controls the relationship between bg1, bg2 and clkout. this pin swings between sgnd and intv cc . pllin/ mode ( pin 5): external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, it will force the controller into forced continuous mode of operation and the phase-locked loop will force the rising bg1 signal to be synchronized with the rising edge of the external clock. when not synchronizing to an external clock, this input, which acts on both controllers, determines how the ltc3788 operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100 k resistor to ground also invokes burst mode operation when the pin is floated. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.2 v and less than intv cc C 1.3 v selects pulse-skipping operation. this can be done by adding a 100k resistor between the pllin/mode pin and intv cc . sgnd ( pin 6): signal ground. all small- signal components and compensation components should connect to this ground, which in turn connects to pgnd at a single point. run1, run 2 ( pin 7, pin 8): run control input. an external resistor divider connects to v in and sets the thresholds for converter operation with a threshold of 1.28 v. once run- ning, a 4.5 a current is sourced from the run pin allowing the user to program hysteresis using the resistor values. maximum current sense threshold vs duty cycle charge pump charging current vs operating frequency duty cycle (%) 0 maximum current sense voltage (mv) 80 100 70 60 40 20 40 10 90 30 50 80 60 100 20 0 120 3788 g25 i lim = intv cc i lim = float i lim = gnd operating frequency (khz) 50 0 charge pump charging current (a) 20 30 80 50 250 450 550 10 60 70 40 150 350 650 750 3788 g26 t = 130c t = 25c t = ? 45c v sw = 12v v boost ? v sw = 4.5v
ltc3788 10 3788fc p in func t ions pgood2 (pin 14): power good indicator for channel 2. open-drain logic output that is pulled to ground when the output voltage is more than 10% away from the regulated output voltage. to avoid false trips the output voltage must be outside the range for 25 s before this output is activated. intv cc (pin 19): output of internal 5.4 v ldo. power supply for control circuits and gate drives. decouple this pin to gnd with a minimum 4.7 f low esr tantalum or ceramic capacitor. extv cc (pin 20): external power input. when this pin is higher than 4.8 v an internal switch bypasses the internal regulator and supply power to intv cc directly from extv cc . pgnd (pin 21): driver power ground. connects to the sources of bottom ( main) n-channel mosfets and the (C) terminal(s) of c in and c out . vbias (pin 22): main supply pin. it is normally tied to the input supply v in or to the output of the boost converter. a bypass capacitor should be tied between this pin and the signal ground pin. the operating voltage range on this pin is 4.5v to 38v (40v abs max). bg1, bg 2 (pin 23, pin 18): bottom gate. connect to the gate of the main nmos . boost 1, boost2 (pin 24, pin 17): floating power supply for the synchronous nmos. bypass to sw with a capacitor and supply with a schottky diode connected to intv cc . tg1, tg 2 (pin 25, pin 16): top gate. connect to the gate of the synchronous nmos. sw1, sw 2 (pin 26, pin 15): switch node. connect to the source of the synchronous nmos, the drain of the main nmos and the inductor. pgood1 (pin 27): power good indicator for channel 1. open-drain logic output that is pulled to ground when the output voltage is more than 10% away from the regulated output voltage. to avoid false trips the output voltage must be outside the range for 25 s before this output is activated. ilim (pin 28): current comparator sense voltage range input. this pin is used to set the peak current sense volt- age in the current comparator. connect this pin to sgnd, open and intv cc to set the peak current sense voltage to 50mv, 75mv, and 100mv, respectively. ss1, ss 2 (pin 29, pin 13): output soft-start input. a capacitor to ground at this pin sets the ramp rate of the output voltage during start-up. ith1, ith 2 (pin 30, pin 12): current control threshold and error amplifier compensation point. the voltage on this pin sets the current trip threshold. vfb1, vfb2 (pin 31, pin 11): error amplifier feedback input. this pin receives the remotely sensed feedback voltage from an external resistive divider connected across the output. sense1 + , sense2 + (pin 32, pin 10): positive current sense comparator input. the (+) input to the current comparator is normally connected to the positive terminal of a current sense resistor. the current sense resistor is normally placed at the input of the boost controller in series with the inductor. this pin also supplies power to the current comparator. gnd ( exposed pad pin 33): ground. the exposed pad must be soldered to the circuit board for rated thermal performance.
ltc3788 11 3788fc switching logic and charge pump + ? 4.8v 3.8v vbias v in c in intv cc pllin/ mode pgood + ? 1.32v 1.08v + ? ? ? + ? + vfb extv cc 5.4v ldo vco pfd sw 0.425v sens lo boost tg c b c out v out d b clkout pgnd bg intv cc vfb s r q ea 1.32v ss 1.2v r sense 0.5a/ 4.5a 10a 11v shdn ? + shdn 2.5v ? + r c ss sens lo ith c c c ss c c2 0.7v 2.8v slope comp 2mv + ? ? + sense ? sense + sleep shdn clk2 clk1 run sgnd intv cc freq duplicate for second controller channel + ? + ? l + ? en 5.4v ldo en 20a 100k sync det ilim phasmd ov 3788 bd current limit b lock diagra m
ltc3788 12 3788fc o pera t ion main control loop the ltc3788 uses a constant-frequency, current mode step- up architecture with the two controller channels oper - ating 180 or 240 degrees out-of-phase ( depending on the phasmd pin connection). during normal operation, each external bottom mosfet is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, icmp, resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the ith pin, which is the output of the error amplifier ea. the error amplifier compares the output voltage feedback signal at the vfb pin, ( which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 1.200 v reference voltage. when the load cur- rent increases, it causes a slight decrease in v fb relative to the reference, which causes the ea to increase the i th voltage until the average inductor current matches the new load current. after the bottom mosfet is turned off each cycle, the top mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.8v, the vbias ldo (low dropout linear regulator) supplies 5.4 v from vbias to intv cc . if extv cc is taken above 4.8 v, the vbias ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies 5.4v from extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source such as one of the ltc3788 switching regulator outputs. shutdown and start-up (run1, run2 and ss1, ss2 pins) the two channels of the ltc3788 can be independently shut down using the run1 and run2 pins. pulling either of these pins below 1.28 v shuts down the main control loop for that controller. pulling both pins below 0.7 v disables both controllers and most internal circuits, including the intv cc ldos. in this state, the ltc3788 draws only 8a of quiescent current. the run pin may be externally pulled up or driven directly by logic. when driving the run pin with a low impedance source, do not exceed the absolute maximum rating of 8v. the run pin has an internal 11 v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage ( for example, v in ), as long as the maximum current into the run pin does not exceed 100a. the start-up of each controllers output voltage v out is controlled by the voltage on the ss pin for that channel. when the voltage on the ss pin is less than the 1.2 v in- ternal reference, the ltc3788 regulates the v fb voltage to the ss pin voltage instead of the 1.2 v reference. this allows the ss pin to be used to program a soft-start by connecting an external capacitor from the ss pin to sgnd. an internal 10 a pull-up current charges this capacitor creating a voltage ramp on the ss pin. as the ss voltage rises linearly from 0 v to 1.2 v ( and beyond up to intv cc ), the output voltage v out rises smoothly to its final value. light load current operationburst mode operation, pulse-skipping or continuous conduction ( pllin/mode pin) the ltc3788 can be enabled to enter high efficiency burst m ode operation, constant - frequency pulse- skipping mode or forced continuous conduction mode at low load currents. to select burst mode operation, tie the pllin/ mode pin to a ground ( e.g., sgnd). to select forced continuous operation, tie the pllin/mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.2v and less than intv cc C 1.3v. when a controller is enabled for burst mode operation, the minimum peak current in the inductor is set to approxi- mately 30% of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier ea will decrease the voltage on the ith pin. when the i th voltage drops below 0.425 v, the internal sleep signal goes high ( enabling sleep mode) and both external mosfets are turned off. (refer to block diagram)
ltc3788 13 3788fc o pera t ion in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc3788 draws. if one channel is shut down and the other channel is in sleep mode, the ltc3788 draws only 125 a of quiescent current. if both channels are in sleep mode, the ltc3788 draws only 200 a of quiescent current. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the ith pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the bottom external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator ( ir) turns off the top external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous current operation. in forced continuous operation or when clocked by an external clock source to use the phase-locked loop (see the frequency selection and phase-locked loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur- rent is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous operation has the advantages of lower output voltage ripple and less interference to audio circuitry, as it maintains constant-frequency operation independent of load current. when the pllin/ mode pin is connected for pulse- skipping mode, the ltc3788 operates in pwm pulse-skipping mode at light loads. in this mode, constant-frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator i cmp may remain tripped for several cycles and force the external bottom mosfet to stay off for the same number of cycles ( i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3788s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to sgnd, tied to intv cc , or programmed through an external resistor. tying freq to sgnd selects 350 khz while tying freq to intv cc selects 535 khz. placing a resistor between freq and sgnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 6. a phase-locked loop ( pll) is available on the ltc3788 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the ltc3788s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn-on of the first controllers external bottom mosfet to the rising edge of the synchronizing signal. thus, the turn - on of the second controller s external bottom mosfet is 180 or 240 degrees out-of-phase to the rising edge of the external clock source. the vco input voltage is prebiased to the operating fre- quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of bg1. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency. the typical capture range of the ltc3788s pll is from approximately 55 khz to 1 mhz, and is guaranteed to lock to an external clock source whose frequency is be- tween 75khz and 850khz.
ltc3788 14 3788fc o pera t ion the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.2v (falling). polyphase applications (clkout and phasmd pins) the ltc3788 features two pins ( clkout and phasmd) that allow other controller ics to be daisychained with the ltc3788 in polyphase ? applications. the clock output signal on the clkout pin can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or multiple separate outputs. the phasmd pin is used to adjust the phase of the clkout signal as well as the relative phases between the two internal controllers, as summarized in table 1. the phases are calculated relative to the zero degrees phase being defined as the rising edge of the bottom gate driver output of controller 1 (bg1). table 1. v phasmd controller 2 phase (c) clkout phase (c) gnd 180 60 floating 180 90 intv cc 240 120 clkout is disabled when one of the channels is in sleep mode and another channel is either in shutdown or in sleep mode. operation when v in > v out when v in rises above the regulated v out voltage, the boost controller can behave differently depending on the mode, inductor current and v in voltage. in forced con- tinuous mode, the loop works to keep the top mosfet on continuously once v in rises above v out . the internal charge pump delivers current to the boost capacitor to maintain a sufficiently high tg voltage. in pulse-skipping mode, if v in is between 100% and 110% of the regulated v out voltage, tg turns on if the inductor current rises above a certain threshold and turns off if the inductor current falls below this threshold. this threshold current is set to approximately 6%, 4% or 3% of the maximum i lim current when the ilim pin is grounded, floating or tied to intv cc , respectively. if the controller is programmed to burst mode operation under this same v in window, then tg remains off regardless of the inductor current. if v in rises above 110% of the regulated v out voltage in any mode, the controller turns on tg regardless of the inductor current. in burst mode operation, however, the internal charge pump turns off if the entire chip is asleep ( the other channel is asleep or shut down). with the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient tg voltage needed to keep the top mosfet completely on. to prevent excessive power dissipation across the body diode of the top mosfet in this situation, the chip can be switched over to forced continuous mode to enable the charge pump, or a schottky diode can also be placed in parallel to the top mosfet. power good the pgood1, 2 pin is connected to an open-drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood1, 2 pin low when the corresponding vfb1, 2 pin voltage is not within 10% of the 1.2 v refer- ence voltage. the pgood1, 2 pin is also pulled low when the corresponding run1, 2 pin is low ( shut down). when the vfb1, 2 pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. operation at low sense pin common voltage the current comparator in the ltc3788 is powered directly from the sense + pin. this enables the common mode voltage of sense + and sense C pins to operate at as low as 2.5 v, which is below the uvlo threshold. the figure on the first page shows a typical application when the controllers vbias is powered from v out while v in supply can go as low as 2.5 v. if the voltage on sense + drops below 2.5 v, the ss pin will be held low. when the sense voltage returns to the normal operating range, the ss pin will be released, initiating a new soft-start cycle. boost supply refresh and internal charge pump each top mosfet driver is biased from the floating bootstrap capacitor c b , which normally recharges during each cycle through an external diode when the bottom
ltc3788 15 3788fc mosfet turns on. there are two considerations to keep the boost supply at the required bias level. during start-up, if the bottom mosfet is not turned on within 100s after uvlo goes low, the bottom mosfet will be forced to turn on for ~400 ns. this forced refresh gener- ates enough boost-sw voltage to allow the top mosfet ready to be fully enhanced instead of waiting for the initial few cycles to charge up. there is also an internal charge pump that keeps the required bias on boost. the charge pump always operates in both forced continuous mode and pulse-skipping mode. in burst mode operation, the charge pump is turned off during sleep and enabled when the chip wakes up. the internal charge pump can normally supply a charging current of 55a. o pera t ion the typical application on the first page is a basic ltc3788 application circuit. ltc3788 can be configured to use either inductor dcr ( dc resistance) sensing or a discrete sense resistor (r sense ) for current sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it does not require current sensing resistors and is more power-efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense ( if r sense is used) and inductor value. next, the power mosfets are selected. finally, input and output capacitors are selected. sense + and sense C pins the sense + and sense C pins are the inputs to the cur- rent comparators. the common mode input voltage range of the current comparators is 2.5 v to 38 v. the current sense resistor is normally placed at the input of the boost controller in series with the inductor. the sense + pin also provides power to the current comparator. it draws ~200 a during normal operation. there is a small base current of less than 1 a that flows into the sense C pin. the high impedance sense C input to the current comparators allow accurate dcr sensing. filter components mutual to the sense lines should be placed close to the ltc3788, and the sense lines should run close together to a kelvin connection underneath the current sense element ( shown in figure 1). sensing cur- figure 1. sense lines placement with inductor or sense resistor a pplica t ions i n f or m a t ion rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2 b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. sense resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 2 a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) . when the ilim pin is grounded, floating or tied to intv cc , the maximum threshold is set to 50mv, 75mv or 100 mv, respectively. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current , ?i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 v in to sense filter, next to the controller inductor or r sense 3788 f01
ltc3788 16 3788fc a pplica t ions i n f or m a t ion always the same and varies with temperature. consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ). next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/c . a conservative value for the maximum inductor temperature (t l(max) ) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0.1 f to 0.47f. this forces r1|| r2 to around 2 k, reducing error that might have been caused by the sense + pins 1a current. (2a) using a resistor to sense current (2b) using the inductor dcr to sense current figure 2. tw o different methods of sensing current tg sw bg inductor dcr l ltc3788 intv cc boost sense + sense ? r2c1 r1 vbias v in v out place c1 near sense pins sgnd 3788 f02b (r1 || r2) ? c1 = l dcr r sense(eq) = dcr ? r2 r1 + r2 tg sw bg ltc3788 intv cc boost sense + sense ? (optional) vbias v in v out sgnd 3788 f02a when using the controller in low v in and very high voltage output applications, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for boost regulators operating at greater than 50% duty factor. a curve is provided in the typical performance characteristics section to estimate this reduction in peak output current level depending upon the operating duty factor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc3788 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2 b. the dcr of the inductor can be less than 1m for high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor could reduce the efficiency by a few percent compared to dcr sensing. if the external r1||r t c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r 2/(r 1 + r 2). r 2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not
ltc3788 17 3788fc a pplica t ions i n f or m a t ion the equivalent resistance r1|| r2 is scaled to the room temperature inductance and maximum dcr: r1|| r2 = l (dcr at 20 c) ? c1 the sense resistor values are: r1 = r1|| r2 r d ; r2 = r1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at v in = 1/2 v out : p loss r1 = (v out ? v in ) ? v in r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge and switching losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current ?i l decreases with higher inductance or frequency and increases with higher v in : ? i l = v in f ? l 1 ? v in v out ? ? ? ? ? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ?i l = 0.3(i max ). the maximum ?i l occurs at v in = 1/2 v out . the inductor value also has secondary effects. the tran- sition to burst mode operation begins when the average inductor current required results in a peak current below 10% of the current limit determined by r sense . lower inductor values (higher ?i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, because increased inductance requires more turns of wire, copper losses will increase. ferrite core inductors have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura- tion. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet selection tw o external power mosfets must be selected for each controller in the ltc3788: one n-channel mosfet for the bottom ( main) switch, and one n-channel mosfet for the top (synchronous) switch. the peak-to-peak gate drive levels are set by the intv cc voltage. this voltage is typically 5.4 v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5 v); then, sub-logic level threshold mosfets (v gs(th) < 3 v) should be used. pay close attention to the bv dss
ltc3788 18 3788fc a pplica t ions i n f or m a t ion specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode, the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out ? v in v out synchronous switch duty cycle = v in v out the mosfet power dissipations at maximum output current are given by: p main = (v out ? v in )v out v 2 in ? i out(max) 2 ? 1 + ( ) ? r ds(on) + k ? v 3 out ? i out(max) v in ? r dr ? c miller ? f p sync = v in v out ? i out(max) 2 ? 1 + ( ) ? r ds(on) where d is the temperature dependency of r ds(on) and r dr (approximately 1) is the effective driver resistance at the mosfets miller threshold voltage. the constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. both mosfets have i 2 r losses while the bottom n- channel equation includes an additional term for transition losses, which are highest at low input voltages. for high v in the high current efficiency generally improves with larger mosfets, while for low v in the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the bottom switch duty factor is low or during overvoltage when the synchronous switch is on close to 100% of the period. the term (1+ d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c in and c out selection the input ripple current in a boost converter is relatively low ( compared with the output ripple current), because this current is continuous. the input capacitor c in voltage rating should comfortably exceed the maximum input voltage. although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not. be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. the value of the c in is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. the required amount of input capacitance is also greatly affected by the duty cycle. high output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of dc current and ripple current. in a boost converter, the output has a discontinuous current, so c out must be capable of reducing the output voltage ripple. the effects of esr ( equivalent series resistance) and the bulk capacitance must be considered when choos- ing the right capacitor for a given output ripple voltage. the steady ripple voltage due to charging and discharging the bulk capacitance is given by: v ripple = i out(max) ? (v out ? v in(min) ) c out ? v out ? f v where c out is the output filter capacitor. the steady ripple due to the voltage drop across the esr is given by: ? v esr = i l(max) ? esr
ltc3788 19 3788fc a pplica t ions i n f or m a t ion the ltc3788 can also be configured as a 2- phase single output converter where the outputs of the two channels are connected together and both channels have the same duty cycle. with 2- phase operation, the two channels of the dual switching regulator are operated 180 degrees out- of-phase. this effectively interleaves the output capacitor current pulses, greatly reducing the output capacitor ripple current. as a result, the esr requirement of the capacitor can be relaxed. because the ripple current in the output capacitor is a square wave, the ripple current requirements for the output capacitor depend on the duty cycle, the num- ber of phases and the maximum output current. figure 3 illustrates the normalized output capacitor ripple current as a function of duty cycle in a 2- phase configuration. to choose a ripple current rating for the output capacitor, first establish the duty cycle range based on the output voltage and range of input voltage. referring to figure 3, choose the worst-case high normalized ripple current as a percentage of the maximum load current. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient. capacitors are now available with low esr and high ripple current ratings (i.e., os-con and poscap). setting output voltage the ltc3788 output voltages are each set by an external feedback resistor divider carefully placed across the out- put, as shown in figure 4. the regulated output voltage is determined by: v out = 1.2v 1 + r b r a ? ? ? ? ? ? great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. figure 3. normalized output capacitor ripple current (rms) for a boost converter 0.1 i oripple / i out 0.9 3788 f03 0.3 0.5 0.7 0.8 0.2 0.4 0.6 3.25 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 duty cycle or (1-v in / v out ) 1-phase 2-phase figure 4. setting output voltage ltc3788 vfb v out r b r a 3788 f04 figure 5. using the ss pin to program soft-start ltc3788 ss c ss sgnd 3788 f05 soft-start (ss pins) the start-up of each v out is controlled by the voltage on the respective ss pins. when the voltage on the ss pin is less than the internal 1.2 v reference, the ltc3788 regulates the vfb pin voltage to the voltage on the ss pin instead of 1.2v. soft- start is enabled by simply connecting a capacitor from the ss pin to ground, as shown in figure 5. an internal 10a current source charges the capacitor, providing a linear ramping voltage at the ss pin. the ltc3788 will regulate the vfb pin ( and hence, v out ) according to the voltage on the ss pin, allowing v out to rise smoothly from v in to its final regulated value. the total soft-start time will be approximately: t ss = c ss ? 1.2v 10a
ltc3788 20 3788fc a pplica t ions i n f or m a t ion intv cc regulators the ltc3788 features two separate internal p-channel low dropout linear regulators ( ldo) that supply power at the intv cc pin from either the vbias supply pin or the extv cc pin depending on the connection of the extv cc pin. intv cc powers the gate drivers and much of the ltc3788s internal circuitry. the vbias ldo and the extv cc ldo regulate intv cc to 5.4 v. each of these can supply a peak current of 50 ma and must be bypassed to ground with a minimum of 4.7 f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent in- teraction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3788 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the vbias ldo or the extv cc ldo. when the voltage on the extv cc pin is less than 4.8 v, the vbias ldo is enabled. in this case, power dissipation for the ic is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency, as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the ltc3788 intv cc current is limited to less than 40 ma from a 40v supply when not using the extv cc supply: t j = 70c + (40ma)(40v)(34c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.8 v, the v in ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above 4.55 v. the extv cc ldo attempts to regulate the intv cc voltage to 5.4 v, so while extv cc is less than 5.4 v, the ldo is in dropout and the intv cc voltage is approximately equal to extv cc . when extv cc is greater than 5.4 v, up to an absolute maximum of 6v, intv cc is regulated to 5.4v. significant thermal gains can be realized by powering intv cc from an external supply. tying the extv cc pin to a 5 v supply reduces the junction temperature in the previous example from 125c to 77c: t j = 70c + (40ma)(5v)(34c/w) = 77c if more current is required through the extv cc ldo than is specified, an external schottky diode can be added between the extv cc and intv cc pins. make sure that in all cases extv cc vbias. the following list summarizes possible connections for extv cc : extv cc left open ( or grounded). this will cause intv cc to be powered from the internal 5.4 v regulator resulting in an efficiency penalty at high input voltages. extv cc connected to an external supply. if an external supply is available in the 5.4 v to 6 v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. ensure that extv cc < vbias. topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mos- fets. capacitor c b in the block diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet (s ). the reverse breakdown of the external schottky diode must be greater than v in(max) . the external diode d b can be a schottky diode or silicon diode, but in either case it should have low leakage and fast recovery. pay close attention to the reverse leakage at high temperatures where it generally increases substantially.
ltc3788 21 3788fc a pplica t ions i n f or m a t ion each of the topside mosfet drivers includes an internal charge pump that delivers current to the bootstrap capaci- tor from the boost pin. this charge current maintains the bias voltage required to keep the top mosfet on continuously during dropout/overvoltage conditions. the schottky/silicon diodes selected for the topside drivers should have a reverse leakage less than the available output current the charge pump can supply. curves displaying the available charge pump current under different operat- ing conditions can be found in the typical performance characteristics section. a leaky diode d b in the boost converter can not only prevent the top mosfet from fully turning on but it can also completely discharge the bootstrap capacitor c b and create a current path from the input voltage to the boost pin to intv cc . this can cause intv cc to rise if the diode leakage exceeds the current consumption on intv cc . this is particularly a concern in burst mode operation where the load on intv cc can be very small. the external schottky or silicon diode should be carefully chosen such that intv cc never gets charged up much higher than its normal regulation voltage. fault conditions: overtemperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on-chip (such as an intv cc short to ground), the overtemperature shutdown circuitry will shut down the ltc3788. when the junction temperature exceeds approximately 170 c, the overtemperature circuitry disables the intv cc ldo, causing the intv cc supply to collapse and effectively shut down the entire ltc3788 chip. once the junction temperature drops back to approximately 155 c, the intv cc ldo turns back on. long term overstress (t j > 125 c) should be avoided as it can degrade the performance or shorten the life of the part. phase-locked loop and frequency synchronization the ltc3788 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a low pass filter and a voltage-controlled oscillator ( vco). this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the pllin/ mode pin. the turn- on of controller 2 s top mosfet is thus 180 degrees out-of-phase with the external clock. the phase detector is an edge-sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the inter- nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external os- cillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, c lp , holds the voltage at the vco input. typically, the external clock ( on pllin/mode pin) input high threshold is 1.6v , while the input low threshold is 1.2 v. note that the ltc3788 can only be synchronized to an external clock whose frequency is within range of the ltc3788s internal vco, which is nominally 55 khz to 1 mhz. this is guaranteed to be between 75khz and 850khz. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchro- nization frequency. the vcos input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchro- nization. although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks.
ltc3788 22 3788fc a pplica t ions i n f or m a t ion table 2 summarizes the different states in which the freq pin can be used. table 2. freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor dc voltage 50khz to 900khz any of the above external clock phase locked to external clock minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc3788 is capable of turning on the bottom mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on- time limit. in forced continuous mode, if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles but the output will continue to be regulated. more cycles will be skipped when v in increases. once v in rises above v out , the loop works to keep the top mosfet on continuously. the minimum on-time for the ltc3788 is approximately 110ns. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the greatest improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3788 circuits : 1) ic v in current , 2) intv cc regulator current , 3) i 2 r losses , 4) bottom mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typically results in a small (< 0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mos- fets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. 3. dc i 2 r losses. these arise from the resistances of the mosfets, sensing resistor, inductor and pc board traces and cause the efficiency to drop at high output currents. 4. transition losses apply only to the bottom mosfet(s), and become significant only when operating at low input voltages. transition losses can be estimated from: transition loss = (1.7) v out 3 v in i o(max) ? c rss f other hidden losses, such as copper trace and internal battery resistances, can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system-level losses during the design phase. figure 6. relationship between oscillator frequency and resistor value at the freq pin freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3788 f06 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125
ltc3788 23 3788fc a pplica t ions i n f or m a t ion checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load ( esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recov- ery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the ith pin not only allows optimization of control loop behavior, but it also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 9 circuit will provide an adequate starting point for most applications. the i th series rc-cc filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is complete and the particular output capacitor type and value have been determined. the output capacitors must be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 s to 10 s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet and load resistor directly across the output capacitor and driving the gate with an ap- propriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the b andwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by de- creasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed- loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus, a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. design example as a design example for one channel, assume v in = 12v(nominal), v in = 22v ( max), v out = 24 v, i out(max) = 4a, v sense(max) = 75mv, and f = 350khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the plllpf pin to gnd, generating 350 khz operation. the minimum inductance for 30% ripple current is: ? i l = v in f ? l 1 ? v in v out ? ? ? ? ? ? a 6.8 h inductor will produce a 31% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 9.25a.
ltc3788 24 3788fc a pplica t ions i n f or m a t ion the r sense resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: r sense 75mv 9.25a = 0.008 choosing 1% resistors: r a = 5 k and r b = 95.3 k yields an output voltage of 24.072v. the power dissipation on the top side mosfet can be easily estimated. choosing a vishay si7848bdp mosfet results in: r ds(on) = 0.012, c miller = 150pf. at maximum input voltage with t(estimated) = 50c: p main = (24v ? 12v) 24v (12v) 2 ? (4a) 2 ? 1 + (0.005)(50 c ? 25 c) [ ] ? 0.008 + (1.7)(24v) 3 4a 12v (150pf)(350khz) = 0.7w c out is chosen to filter the square current in the output. the maximum output current peak is: i out(peak) = 4 ? 1 + 31% 2 ? ? ? ? ? ? = 4.62a a low esr (5 m?) capacitor is suggested. this capacitor will limit output voltage ripple to 23.1mv ( assuming esr dominate ripple). pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 7. figure 8 illustrates the current waveforms present in the various branches of the 2- phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. put the bottom n- channel mosfets mbot1 and mbot2 and the top n-channel mosfets mtop1 and mtop2 in one compact area with c out . 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the path formed by the bottom n-channel mosfet and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other. 3. do the ltc3788 vfb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground and placed close to the vfb pin. the feedback resistor connections should not be along the high cur- rent input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers cur- rent peaks. an additional 1 f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes ( sw1, sw2), top gate nodes (tg1, tg2) and boost nodes ( boost1, boost2) away from sensitive small- signal nodes, especially from the opposites channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and, therefore, should be kept on the output side of the ltc3788 and occupy a minimal pc trace area . 7. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic.
ltc3788 25 3788fc a pplica t ions i n f or m a t ion pc board layout debugging start with one controller on at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node ( sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output volt- age. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typically 10% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug- gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particu- larly difficult region of operation is when one controller channel is nearing its current comparator trip point while the other channel is turning on its bottom mosfet. this occurs around the 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation with high duty cycle. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. an embarrassing problem, which can be missed in an otherwise properly working switching regulator results when the current sensing leads are hooked up backwards. the output voltage under this improper hook-up will still be maintained , but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage.
ltc3788 26 3788fc a pplica t ions i n f or m a t ion figure 7. recommended printed circuit layout diagram sense1 + sense1 ? sense2 + sense2 ? vfb1 ith1 sgnd extv cc run1 run2 freq ss2 vfb2 ss1 pllin/mode pgood1 pgood2 tg1 sw1 boost1 bg1 vbias intv cc pgnd bg2 tg2 boost2 sw2 c b1 c b2 v in v out1 v out2 ltc3788 l2 l1 m2 m3 3788 f07 v pull-up v pull-up r sense1 r sense2 m1 m4 gnd ith2 ilim phsmd clkout + f in + +
ltc3788 27 3788fc figure 8. branch current waveforms r l1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 bold lines indicate high switching current. keep lines to a minimum length. sw2 3788 f08 v out2 c out2 l2 r sense2 a pplica t ions i n f or m a t ion
ltc3788 28 3788fc a pplica t ions i n f or m a t ion figure 9. high efficiency 2-phase 24v boost converter sense1 + sense1 ? sense2 + sense2 ? vfb1 ith1 sgnd extv cc run1 run2 freq ss2 vfb2 ss1 pllin/mode pgood1 pgood2 tg1 sw1 boost1 bg1 vbias intv cc pgnd bg2 tg2 boost2 sw2 c b1 0.1f c b1 0.1f 100k c int 4.7f v in 5v to 24v v out 24v, 10a* ltc3788 r a1 12.1k r b1 232k r ith1 8.66k c ith1 15nf c ss1 0.1f c ith1 220pf l2 3.3h l1 3.3h mbot1 mbot2 3788 f09 intv cc r sense1 4m r sense2 4m ith2 phsmd ilim clkout mtop2 mtop1 c outa1 22f 4 c outb1 220f c ina 22f 4 c inb 220f c outa2 22f 4 c outb2 220f cina, couta1, couta2: sanyo, 50ce220ax cinb, coutb1, coutb2: tdk c4532x5r1e226m l1, l2: pulse pa1494.362nl mbot1, mbot2, mtop1, mtop2: renesas hat2169h *when v in < 8v, maximum load current available is reduced. + + +
ltc3788 29 3788fc a pplica t ions i n f or m a t ion figure 10. high efficiency dual 24v/48v boost converter with inductor dcr current sensing sense1 ? sense1 + sense2 + sense2 ? vfb1 ith1 sgnd extv cc run1 run2 freq ss2 vfb2 ss1 pllin/mode pgood1 pgood2 tg1 sw1 boost1 bg1 vbias intv cc pgnd bg2 tg2 boost2 sw2 r s2 26.1k, 1% c outa2 : c4532x7r1h685k c outb2 : sanyo 63ce220kx c ina , c outa1 : tdk c4532x5r1e226m c inb , c outb1 : sanyo 50ce220ax l1: pulse pa2050.103nl l2: pulse pa2050.163nl mbot1, mtop1: renesas rjk0305 mbot2a, mbot2b, mtop2: renesas rjk0652 d3: diodes inc b340b d4: diodes inc b360a r b1 232k 1% c ith1 , 220pf c ss1 , 0.01f c ss2 , 0.1f c ith1 , 15nf c int 4.7f c b1 , 0.1f c b1 , 0.1f d1 v in 5v to 24v d2 ltc3788 l2 16h l1 10.2h mtop1 mbot2a mbot2b mbot1 mtop2 3788 f10 100k 100k intv cc d4 d3 c ina 22f 4 c inb 220f v out1 24v, 4a c outa1 6.8f 4 c outb1 220f v out2 48v, 2a c outa2 22f 4 c outb2 220f r s4 30.1k, 1% r a1 12.1k, 1% r a2 12.1k, 1% r freq 41.2k r ith1 8.87k, 1% ith2 c ith2 , 4.7nf c ith2a 220pf r ith2 23.7k, 1% ilim phsmd clkout c3 0.1f r b2 475k 1% r s1 53.6k, 1% r s3 42.2k, 1% c1 0.1f c2 0.1f c4 0.1f intv cc + + +
ltc3788 30 3788fc p ackage descrip t ion uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc3788 31 3788fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 4/10 updates to typical application. updates in the electrical characteristics section. updates to pllin/mode in pin functions. updates to application information. new figure 9 added. updated note on typical application. updated related parts table. 1 3, 4 9 21, 24 28 32 32 b 9/11 updated the topside mosfet driver supply (c b , d b ) section. updated the related parts. 21 32 c 1/12 revised figure 10 29
ltc3788 32 3788fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2009 lt 0112 rev c ? printed in usa typical a pplica t ion r ela t e d p ar t s sense1 ? sense1 + sense2 + sense2 ? vfb1 ith1 sgnd extv cc run1 run2 freq ss2 vfb2 ss1 pllin/mode pgood1 pgood2 tg1 sw1 boost1 bg1 vbias intv cc pgnd bg2 tg2 boost2 sw2 c ina , c outa1 , c outa2 : sanyo, 50ce220ax c inb , c outb1 , c outb2 : tdk c4532x5r1e226m l1: pulse pa1494.362nl l2: pulse pa1294.132nl mbot1, mbot2, mtop1, mtop2: renesas hat2169h * when v in = 8v, maximum load current available is reduced. v out2 follows v in when v in > 12v. r b1 232k c ith1 , 220pf c ss1 , 0.1f c ss2 , 0.1f c ith1 , 15nf c int 4.7f c b1 , 0.1f c b1 , 0.1f d1 v in 5v to 24v d2 ltc3788 l2 1.25h l1 3.3h mtop1 mbot2 mbot1 mtop2 3788 ta02 100k 100k intv cc c ina 22f 4 c inb 220f v out1 24v, 5a c outa1 22f 4 r sense1 4m r sense2 3m c outb1 220f v out2 12v, 10a* c outa2 22f 4 c outb2 220f r a1 12.1k r a2 12.1k r ith1 8.66k ith2 c ith2 , 15nf c itha2 , 100pf r ith2 2.7k ilim phsmd clkout r b2 110k + + + high efficiency dual 12v/24v boost converter part number description comments ltc3787/ ltc3787-1 multiphase, dual channel synchronous step-up controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, 50khz to 900khz fixed operating frequency, 4mm 5mm qfn-28, ssop-28 ltc3786 low i q synchronous step-up controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, 50khz to 900khz fixed operating frequency, 3mm 3mm qfn-32, msop-16e ltc3862/ ltc3862-1 multiphase, dual channel single output current mode step-up dc/dc controller 4v v in 36v, 5v or 10v gate drive, 75khz to 500khz fixed operating frequency, ssop-24, tssop-24, 5mm 5mm qfn-24 ltc3859a low i q , triple output buck/buck/boost synchronous dc/dc controller all outputs remain in regulation through cold crank, 4.5v (down to 2.5v after start-up) v in 38v, v out(buck) up to 24v, v out(boost) up to 60v, i q = 55a ltc3789 high efficiency synchronous 4-switch buck-boost dc/dc controller 4v v in 38v, 0.8v v out 38v, ssop-28, 4mm 5mm qfn-28, ssop-28

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